Data checking system



June 3, 1969 1. VERHQEFFA 3,448,254

DATA CHI-:CKING SYSTEM Filed Ju1y 28, 1965 sheet of 11 FIG.I

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Y DATA GHEGKING SYSTEM Filed July 28. 1965 sheet 6 or 11 FIG? 5/ 6/ 1 L FIGS 5/ FIGS {www1-Lim June 3, 1969 .1. VERHOEFF 3,448,254

DATA CHECKING SYSTEM Filed July 28, 1965 Sheet (a of 1l A/U -/2// fr0/f G M3 June 3, 1969 1. vERHor-:FF 3,448,254

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June 3, 1969 J VERHOEFF 3,448,254

DATA CHECKING SYSTEM Filed July 28, 1965 sheet 9 of 11 FIG. lab

June 3, 1969 1. VERHOEFF DATA CHECKING SYSTEM Sheet /0 of 11 Filed July 28, 1965 Filed July 28. 1965 H of 11 Sheet United States Patent() U.S. Cl. 23S-153 14 Claims ABSTRACT F THE DISCLOSURE Apparatus for checking a digital group of the characters selected from a total of 41114-2 different characters comprises a modulo-2 circuit for determining the relation c/d wherein c is the modulo-2 Sum of the number of entered digit positions independent of the value of the digit positions and d is indicative of the modulo-2 sum of the number of entered digit positions whose number value is atleast 21114-2. A modulo-(2111+2) alegbraic adding circuit responds to all digit values of the entered characters. The modulo-2 logic circuit is in controlling connection with the adding circuit for controlling its algebraic sense 1n dependence upon a given condition of the c/d relation whereby when a character group is entered, the result of the algebraic addition and the c/d relation then reached are conjointly indicative of a singular check symbol from among the 41114-2 characters. The check symbol, when digitally added to the entered group, causes the result of the algebraic addition and the c/d relation to be in accordance with a predetermined checking condition.

My invention relates to methods and means for detecting information errors in data processing equipment. More specifically, the invention relates to methods and means for checking a group or digital sequence of characters individualy selected from a total of 41114-2 different characters having respective fixed values, wherein m iS at least equal to the value 2, and wherein to each such group of characters there is added a check symbol selected from the same number of 41114-2 available characters. Upon introduction of the character group with its check symbol, the resulting response of the checking device is indicative of the accuracy or inaccuracy of the group.

For illustration of the term 41114-2, it will be seen that in a decimal number, the value of 111 is equal to 2, so that 4m+2:10, corresponding to the ten values O 9 available for each individual `digit position. For an alphabetic group with a total of 26 different characters, the value of 111 would be 111:6.

A checking device, intended exclusively for 111:2 and consequently for checking a decimal number, is known from the German Patent 1,025,180. The device is supplied with a character group to which a check symbol is added. If the group of characters is correct, the device reaches a given ultimate state. If an error was made when entering a group of characters, for example by mutually exchanging two sequential characters, this ultimate state of the device does not come about. Diiculties are encountered in two cases, namely for 111:2 (decimal numbers) and for 111:6 (alphabetic groups).

Thus, in a self-checking device according to Netherlands Patent 100,613 or U.S. Patent 3,138,701 for use with decimal numbers (111:2), an eleventh digit symbol is used as a check symbol. While the checking pertormance of such a device is satisfactory, it has the serious shortcoming of requiring an additional symbol since no eleventh digit symbol is available in the decimal system.

For character groups exclusively consisting of alpha- TCC betic letters so that 111:6, no satisfactory checking method is known if use is made only of the letters available in the alphabet.

There is also a device for 111:2 according to German Patent 1,025,180 which does not need an additional symbol, but in this case the checking performance leaves much to be desired. For example, when a number is being entered into such a device, equipped with two counters, diterent digit numerals may result in one and the same sum of the numerals determined by the respective iiual states of the counters. For example, when the numerals 4 and 8 are entered into the counters having respective base val-ues 3 and 5, and the sum results in the checking numeral, no distinction can be made between the number 81 19 and the number 81 19.

Nor is the checking satisfactory with the method of the International Business Machines Corporation (see `the Preliminary Manual for Self-Checking Number Device or Types 24-26 Card Punches, `form 22-60220; pages 4 5) for 111:2, because a confusion between sequential numerals 0 and 9 cannot be ascertained by this method. Roger L. Sisson, in his paper An Improved Decimal Redundancy Check published in Communications of the Association for Computing Machinery, Volume 1 (1958), No. 5, page 10, has stated that a checking system with ten characters, which ascertains all possible confusions of two sequential numerals does not exist.

It is an object of my invention to devise a method and means for checking a character group whose characters are `selected from a (4111+2)number of different characters, and which aiords a complete checking for errors such as the faulty entering of a character or a confusion between two sequential characters, without the necessity of adding a checking symbol extraneous to the digital system being used. Another object of my invention, additional to the one mentioned above, is to devise a selfchecking system that affords a multiple choice of checking conditions, such as an initially free choice of up to ten such diiierent conditions for a decimal system, thus permitting, for example, the use of a selected one matrix of single-digit check numbers at one locality (for instance one of the branches of a bank or business) and a selected diierent check-number matrix at another locality, with the eect that a multi-digit number (such as a customer account number) which is correct at one locality will be checked as incorrect at the other locality.

Still another object of the invention is to devise a selfchecking system, which aside from meeting the abovestated objects, also atiords a subsequent increase in the number of digit positions without rendering the originally adopted checking symbols obsolete, this being of value, for example, if changes in business require changing from 10-position to 12-position keyboards in the accounting machines or other business equipment being used, thus requiring that zeroes (0) be added in front of pre-existing account numbers without affecting the check digits of those numbers.

To achieve these objects, and in accordance with my invention, I derive by preferably electrical logic means two binary (modulo-2) components (c and d) from a mechanically or electrically entered digital group formed of up to 41114-2 different characters, 111 being an integer, and algebraically add in modulus 2m-l-2, also by logic means, the digit values of the entire group while controlling the or sense of the .algebraic addition in dependence upon the (c/d) relation of the two binary components, whereupon the result of the algebraic addition in conjunction with the ultimate condition of one or both of the modulo-2 components are indicative of the check symbol to be added as a-digit to the group, or-if the group already contains the check digit-are indicative of whether or not the entere-d group is correct. One of the binary components just mentioned corresponds to a modulo-2 count of the digit positions of the character group being entered, or may be looked upon as simply showing by its 1 or 0 state whether the number of digit positions is odd or even. The other modulo-2 component essentially corresponds to a modulo-2 count of those digit positions whose value is above 2m-l-2.

As will appear from the mathematical explanations given below, my invention may also be looked upon as providing a logic method -and system for modulo-2 addition to binary components of the values represented by the respective characters, and for modulo-(Zm-l-l) algebraic addition of the differences between the successive pairs of (2m.-}-1)ary components of these values, the base m being any desired integer, and the (-1- or sign preceding the difference between the (2j)-th and the (2j-Myth of the (2111+1)ary components being determined by 1 inthe exponent equal to the sum of the binary components of the first 2j symbols, Iand by a function of the binary components which respectively does not, or does, change the result of the modulo- (2m-1-1) addition when an exchange occurs between two successive symbols having the same or different binary components respectively (i=1, 2 n).

According to a more specic feature of the invention, the above-mentioned function of the binary components may be formed by the algebraic sum of the double binary components of the value assigned to each (ZD-th symbol and maybe provided with a (-lor sign opposed to one preceding the difference between the (2j)th and the (2j-|-1)th of the (2m--l)ary components.

In the embodiments of my invention described herein, the base value of m is 2 for a character group constituting a decimal number, and the symbols 1 9 have the corresponding numerical values, whereas the symbol denotes the value 10. However, the numerical values assigned to the symbols 1 9, 0 may also differ from the respective values usually ascribed thereto, as will be explained hereinafter.

According to other more specific features of my invention, here initially briefly described with parenthetical reference to FIG. 1 of the drawing, but more fully explained in a later place, an apparatus for checking entered or transmitted data receives the characters of the group as well as the check symbol in form of sequential pulses in a number which determine the value of each character; and these pulses are passed through three different paths, namely first to a pulse-detecting timer member or discriminator G1 which responds to the presence of such a pulse sequence and passes it to first cyclical counter C1, such as a binary ring counter. Secondly, the pulses are supplied to a limit counter B1 which occupies its final counting state upon receiving six or more pulses. Thirdly, the pulses are also applied to a moduloring counter A1. The output voltage pulses from the cyclical counter C1 and the limit counter B1 together with those from the discriminator G1 act through a coincidence gate circuit E1 to control the input of a second cyclical binary counter D1 for modulo-2 addition of binary components of the digit numerals to the number (character group) to be checked. The second modulo-2 ring counter has its output connected to the above-mentioned cyclical counter A1 in modulus 5 to perform an algebraic addition, relative to which the (t-lor sign is determined by the result of the modulo-2 addition of the respective counting stages to which the two binary ring counters C1, D1 have been set.

The supply of a group of characters and of the check symbol in form of successive pulse sequences is known from Netherlands Patent 86,715 showing an apparatus on the elevens-type checking principle, which requires providing a special symbol for the tenth check symbol. This check symbol is constituted by an idle signal, so that the corresponding pulse sequence counts 0 pulses. The use of such a device for checking telephone numbers, for example, has the result that the numbers are unequal in length which entails a variety of difficulties.

It is further known from Netherlands Patent 101,294 to indicate the sign of an addition by the state of a bistable iiip-flop network.

According to another alternative feature of my invention, the numerals or other characters of the group and the check symbol are entered in parallel relation, namely in form of a pulse through respective lines assigned to the different numerical values (FIG. 2), and these pulses are passed through four different paths, namely to a Iirst cyclical counter C2 in 4modulus 2, then to a second cyclical counter D2 in modulus 2 for modulo-2 addition of the binary components of the numerals in the number (character group) to be checked. The pulse sequences are further supplie/d through the respective lines to corresponding inputs of a code converter H2 which has further inputs connected with the outputs of the counters C2 and D2, the code converter having four outputs connected with the inputs of a cyclical quinary counter A2 for modulo-5 algebraic addition, in order to determine the number of the counter stages. If the number, including the check symbol, is correct, the last occurring pulse through a lead common to counters will set them to the prescribed set of ychecking conditions; but if the number is incorrect this state will not be reached.

It may be mentioned that a device operating with parallel entering of numbers and of a checking symbol is known as such from Netherlands Patent 105,499; but this device requires entering more than ten different check symbols with the aid of special keys.

Also known is the skipping of counter stages in a counting device composed of a number of stages connected in cascade and having two stable states. When a pulse is entered, the state of each stage is changed and when a given stage is reached, a pulse is issued to the next following stage. Note the Netherlands Patent 101,- 294.

My invention will be further explained with reference to the accompanying drawing illustrating embodiments of self-checkin g systems according to the invention by way of example, and with reference to accompanying tables.

FIG. l is a logic diagram of a iirst embodiment of the checking system of the present invention for sequential entry of decimal digits.

FIG. 2 is a block diagram of a second embodiment of the checking system of the present invention also relating to the processing of decimal character groups but operating with sequential parallel entry of the digits.

FIG. 3 is a straight-line circuit diagram of a checking system according to FIG. l.

FIGS. 4 to 11 are explanatory pulse diagrams relating to the operation of the system according of FIGS. 1 and 3.

FIG. 12 (divided into FIGS. 12a and 12b) is a circuit diagram of a system corresponding essentially to FIG. 2 but modified for simultaneous parallel entry of digits.

FIG. 13 (divided into FIGS. 13a and 13b) shows circuit details of FIG. 12.

FIG. 14 shows further circuit details of FIG. 12.

FIG. 15 is a pulse diagram relating to the embodiment of FIGS. 12 to 14.

With reference to all of the illustrated embodiments, it appears helpful to rst describe how suitable rules are set up for reliably checking a decimal number, for which nti-:2. The general case of checking a character group in which the characters are chosen from any other (41144-2)- number is then readily derivable by substituting the (2m-|-1)ary component for the quinary component of the value assigned to a numeral.

For determining the check symbol of a digital num'ber in such a way that an error affecting a digit position of the number, or a confusion of respective numerals in two successive digit positions, will always result in a different check symbol so that the error is ascertainable by the checking performance, the numerals that make up the digital number are to be represented in one or another biquinary manner. Assume that the numeral in the -th digit position of a number ai has a binary component el and a quinary component oq. If care is taken that the numerals t) and 1 have respective diierent binary components, then it is also reliably possible-as will be shown further belowto additionally ascertain any error of the type lx in lieu of x0, and hence for example, a confusion of thirteen for thirty, and Vice Versa. An example of a tabulation thus obtainable is shown in Table No. 1

TABLE l Il E eiE0(mod 2) (Equation 1) i=o or if one sets i E ei=r,-(mod 2) i=o then:

If n is odd, then 0 is to be set for uml. In other words the summing operation is stopped when the available variety of numerals is consumed. It will be noted that the second equation comprises a quinary portion in which the coeticients still depend upon the `binary components, and also comprises a binary correcting term. Relative to the latter there still remains some liberty of choice, as will more clearly appear from the following. Hence this corrective term may be chosen in accordance with the requirements of a particular embodiment or purpose.

The illustrated embodiments of equipment are based upon the above-presented equations.

The Equations l and 2 determine the check digit if the n digits of the number have been freely chosen. This is because the Equation 1 determines the binary portion of the check symbol, whereas the Equation 2 determines the quinary portion.

The following applies to the detection of an error:

(1) An error in any individual digit position is always discovered. This is due to the following. If the error changes the binary portion, then the Equation l no longer applies. If the binary portion is not changed, then only the particular a in Equation 2 is changed. The coeicients and the binary portion, being independent of the as, do not change, so that the Equation 2 is no longer satisfied.

(2) A confusion between two successive digits al and i+1 is likewise always discovered. Equation 1 is not affected by such confusion, but Equation 2 changes. To investigate this, we distinguish between two possibilities in which is even and in which i is odd.

Case a: z' is even, hence i=2j The difference between the Value of the left term inV Equation 2 prior to and after the confusion is then However, if e2j=e2j+b then the second term is 0, but the first term is then:

Case b: z is odd, hence i=2i-1.

Under these conditions the difference between the value of the left term in Equation 2b before and after the confusion is as follows:

Again for e2j7e2j 1 the rst term is 0, but the second term now becomes i2(-1"21+70 (mod 5) If e2j=e2j 1, then the second term is again 0, but the rst term is then equal to:

(3) Likewise, a confusion of x0 by lx or vice versa is always discovered. This follows directly from the fact that the binary components of numerals 0 and 1 diier from each other so that the Equation 1 does not remain satisfied.

It follows from the foregoing that the only requirement to 'be exclusively placed by the second equation upon the terms dependent upon s, is that they form a function of e0, e1 en) 4which does not change the modulus 5 if equal lValues of e, and em are exchanged for each other, but which does change the modulus 5 when unequal values of e, and @i+1 are exchanged for each other. Alternative forms of the binary correction member for example are:

Also met is the requirement that the quinary portion of Equatlon 2 remains invariant by exchanging unequal values of e, and sprl.

First embodiment (FIGS. l and 3 toI I] As mentioned, the logic diagram of the iirst embodiment of error detecting equipment according to the invention shown in FIG. 1, is based upon the Equations 1 and 2. -In this apparatus, the symbols, namely the digit numerals of the number to be entered and the check digit, are applied as successive pulse sequences, for example by means of a selector disc K1 corresponding to a telephone dial switch. Such a dial switch may indeed be used for entering telephone numbers. The numeral 0 in this case corresponds to ten pulses.

As mentioned, the apparatus comprises three ring counters A1, C1 :and D1 in the moduli `5, 2 and 2 respectively. Further provided is a counter stage B1 such as a shift register, which upon receipt of six or more pulses on its signal inputs remains in its :linal state reached, whereafter it must be reset Ito the starting state by applying a pulse to a reset input r. The output pulses from counters C1 and B1, as well as the original pulse fromy a timer member G are supplied to respective three inputs of a network gate E1 whose output is connected to the modulo-2 counter D1. A summing device F1 adds the supplied voltage values (0, 1) coming from the outputs of the respective counters C1 and D1. Denoted by L1 and M1 are output devices. Device M1 indicates or signals Whether the number entered by means of the dial switch K1 including the check numeral is correct or faulty. Device L1 indicates the check numeral if only the number has been dialed.

As mentioned, the member G1 responds to the presence of a pulse sequence. The member G1 may consist, for example, of a delayed drop-off relay which is actuated at the commencement of the first pulse of a sequence and whose time delay is large enough to prevent the relay from dropping olf in the pause between each two pulses of the sequence. The timing discriminator G1 thus remains actuated and passes the pulse signals until the entire pulse sequence is terminated. The minimum delay of member G1 corresponds to the number of counting steps in the limit counter B1. For example, the time delay must be sufficient to permit the counter B1 to count fully up to its limit such as six steps.

When a numeral is entered from the dial switch K1 by a corresponding sequence of pulses, the member G1 has responded :and passes the pulse signals to the ring counter C1. This counter counts the pulses of the sequence in modulus 2. The same pulse sequences are also applied to the inputs of the limit counter B1 which counts a maximum of six pulses of a sequence and, after completion of each pulse sequence, is reset to by a pulse received at the reset input r from the timer G1. The ring counter D1 changes its state upon receipt of a sequence of more than five pulses. In other words, the state of the counter D1 represents:

As will be further described in the following, the change in the state of the modulo-2 counter D1 occurs either immediately upon appearance of the sixth pulse or only after the entire pulse sequence is completed, depending upon the state of the modulo-2 counter C1. During the next following appearance of the numeral a0, al 12J- 1, the counter C1 is in the state 2j (mod 2). That is, the counter C1 is then in the starting state. The result of the `above-mentioned modulo-2 addition in summing device F1 determines the sign with which the counter A1 counts the pulses issuing when a numeral is being dialed; and this result, in turn, is determined by the respective states of the counters C1 and D1. Device F1 receives no voltage, and the counter A1 adds if the counters C1 and D1 are both in the starting state or both in the end state; but the device F1 receives voltage and the counter A1 subtracts if the counters C1 :and D1 have respectively different states. The control of counter A1 to operate either additively or subtractively is effected through a control connection f from the output of device Fl. t

After entering of numeral 12J- 1 the counter D1 is at (mod 2) and the sign, with which the counter A1 must count, is then (-l)"2i1.

-Relative to the numeral azj, the following two cases are to be distinguished:

Case a: 623:0, i.e. a2j 6 Since a2j=a2j 1, the sign for the counting operation of the counter A1 is also (-1)21'; and this is the correct sign according to Equation 2b.

The a2,- pulses are correctly counted by counter A1. Counter D1 does not change its state because the counter B1 does not count six pulses. Counter C1 reaches the end state, whereby the voltage in device F1 is changed.

On entering the numeral @2J-+1 it is therefore found that the sign for the activity of the counter A1 is -(-l)21, in accordance with Equation 2b. The numeral 12J-+1 is also counted in the correct sense, irrespective of the value e2j 1. 'I'hat is, if e2j+1=l, then with counter C1 in this end state, the counter yD1 would change its state only after the member G1 had returned to the condition of rest, that is after the entire pulse sequence has been received. Since e2J-=\0, no expedients need be observed for subtracting 2e2j.

The sign is (-1)21-1, whereas it should be the reverse, namely (-1)21, as will appear from a comparison with Equation 2b. Consequently the counter A1 commences to count the pulses in the wrong sense. However, as soon as the counter has received six pulses, the limit counter B1 has reached its end position. Since the ring counter C1 is in the starting state, the counter D1 is reset at this moment, so that the voltage in device F1 isv changed and the counter A1 continues to count in the correct sense. As a result, the counter A1 has ultimately counted the total (*1)2l(2325+12f2j) (mod 5) Counter C1 again resumes the end state, whereby the voltage in device F1 is again changed.

When entering the numeral 12144, the sign for the action of the counter A1 is thus found to be -(-1)"21, which as is required by the Equation 2b.

The entering of a number with a check numeral is supposed to bring the counter A1 to the zero state. As a further criterion, it can be assumed in accordance with Equation 1 that the counter D1 must also be in the zero state. The devices L1 and M1 must then be controlled by the counters A1 and D1. Since the states of respective counters C1 and D1 determine the voltage in summing device F1, the value 0 of this voltage may be taken as a further criterion; that is the accuracy of the equation Effi-#44:0 (mod 2) can thus be checked.

For numbers relative to which n is even, the counter D1 must then be in the end state, and for numerals with an odd n, the counter D1 must -be in the starting state. Such a variant is possible because it is not necessary that the second term of the Equation l assume value O. The control of the members L1 and M1 may also be predicated upon the assumption that this second term has a different, fixed (given) value which is also dependent upon the length of the number.

The circuit diagram shown in FIG. 3 is in accordance with a system built and operating in the above-described manner in a library where the readers are to pick the index numbers of books from catalog cards and dial them on a standard telephone. If the number is correct, the telephone informs the reader of its availability and the approximate waiting time, while the system also signals the number to the attendants in the stock room. -If the number is incorrect, the reader is asked over the telephone to check and redial the number, the infor- Imation in either case being automatically given from tape recordings.

The diagram of FIG. 3 corresponds to the above explained logic diagram of FIG. l, the same reference characters K1, G1, C1, D1, A1, B1, E1, F1 and L1 being used for identifying the main logic components. These components are composed of telephone relays, the switching speed thus obtainable being ample for the intended purpose. The relay coils are denoted by capital letters such as lI, DS, E, A, D, and also by numerals 1, 1', 2, 2', 3, 3. Lower case letters denote relay contacts and are shown in the normally occupied positions. For example, dial switch relay I has three contacts z' in devices G1, E1 and P1 respectively. Contact i in timer device G1 energizes relay DS for each individual pulse, such as for each of the eight pulses when the numeral 8 is being dialed in K1 (FIG. 4). DS has a time-delayed drop-out so as to remain picked up for slightly more than a single pulse duration. Consequently, relay DS stays picked up for the duration of the entire pulse train, for example during all eight pulses denoting the numeral 8 (FIG. 4). DS has two normally open contacts ds in respective devices E1 and C1.

In the binary counter C1, the contact ds applies a single pulse for each complete sequence. Hence the counter C1 counts the number of digit positions or pulse sequences.

A relay P in device F1 is energized under control by contacts h and l of respective relays H and L in counters C1 and D1 so as to be energized only if either relay H or relay L is energized but not when both relays H, L are energized or deenergized simultaneously. Thus the relay P is active only when C1 and D1 are in respectively different counting states. Relay P has three contacts p in the quinary ring counter A1 and one contact p in the check-symbol indicator device L1.

The counter C1 is a dip-flop composed of two differential relays H, G of which one has two coils (H) and the other has three coils (G). Two of the three G coils are cumulative and jointly operate in magnetic opposition to the third G coil, as is indicated by arrows. When contact DS in C1 closes as mentioned above, the two mutually opposed coils H are both excited so that their effects cancel each other, and only one coil G is energized and closes its self-holding g contact which connects the g coil to the plus pole (ground), thus holding this one G coil energized. The other, normally open g contact in C1 closes, but the two other G coils connected thereto remain deenergized because contact h in C1 is open. The G relay then energized, actuates its other g contacts in devices F and L1 to provide a signal of the counting state of C1.

When the pulse sequence from K1 is terminated so that DS drops off and opens the contact DS in C1, the G relay remains energized through its self-holding contact g, and no change occurs in the state of the binary counter C1.

When the next pulse train commences, contact DS in C1 closes. The current through contact DS then flows through contact h and through only one of coils H so that the H relay picks up. It switches the contact lz in C1 and energizes the two left G coils which jointly oppose the energized right coil G. Hence the G relay drops off and its self-holding contact g energizes the second H coil. The H relay remains picked up until shortly after the pulse duration, at which time the Contact ds opens. Since H is picked up, it actuates its contact h in device F1.

The binary counter D1 operates analogously as a 2-bit ip-flop.

The register B1 operating as a 6-bit counter comprises differential relays 1 and 1 which operate as a flip-flop in a manner similar to that explained above with reference to C1. The register further comprises two further flipdlops 2,2 and 3,3. The operation of register B1 is as follows.

The contact ds in device E1 closes at the beginning of a pulse sequence and opens after the termination of a complete sequence, as explained above. Normally the relay I of dial switch K is energized and hence the two relay contacts i in respective devices G1 and E1 are open. The counting pulses from K1 are applied by repeatedly deenergizing the relay I and correspondingly closing these two contacts i.

Thus, the lfirst pulse causes the zcontact to close for the length of the individual pulse and to apply plus potential (ground) through signal lead s1, contacts 2', 3', lead s2, contact 1, lead s2' and contact 1 to both relay coils 1 Whose effects cancel each other, and also through only the left one of coils 1, so that relay 1 is picked up and connects its self-holding contact 1 through contact ds in device El to the plus pole (ground). The second contact 1 in register B also closes, but this has no effect since the two left coils l1 are deenergized.

When the first pulse is terminated and pulse contact i reopens, the left coils 1 and 1' remain energized through lead s2', self-holding contact 1, lead s0 and contact ds. Since now only the left coil of relay 1' is energized, this relay picks up and closes its 1 contacts. After termination of the first pulse, therefore, both relays 1 and 1 are picked up. That is, the flip-flop 1-1 is then in the on state, as is indicated in Table 2.

TABLE 2 States of Flip-Flops in Register B1 Digit Value The second pulse again causes contact i to close. This energizes both coils 2' and the left coil 2 of the second flip-flop through i-s1-s2-1-s3-s3. Relay 2 picks up and closes its self-holding contact 2. When the second pulse is terminated and the z' Contact opens, the right coil 2' is no longer energized, whereas the left coil 2' remains energized through ds-s0-2-s3 so that the 2' relay picks up and closes its contact 2' connecting lead s3 with lead s4. The second flip-flop 2-2 is then in the on state. The first flip-flop 1-1', however, has been reset to off condition because the second pulse also energized the right coils 1, so that all three .1 coils were active and magnetically cancelled their effects to make the 1 relay drop olf.

In lieu of a further description of details, apparent to those skilled in the art from the foregoing explanations in conjunction with the circuit diagram of FIG. 3, reference is made to Table 2 and FIG. 4 which conjointly represent the counting operation of register B1 in a synoptic and more readily understandable fashion. FIG. 4 relates to a sequence of eight pulses denoting number 8 which is dialed in device K1 and causes the relay I to drop olf eight times, as is schematically indicated in the uppermost pulse-time graph of FIG. 4. As shown, the relay DS in device G1 remains energized slightly longer than the entire duration of all eight pulses. The pulse contact i issues eight pulses to lead s1. It will be noted that the relay I in conjunction with its contact i operates as an inverter which inverts the signals of the relay I in device K1. Indicated in FIG. 4 are the occurrence and duration of the pulses appearing on leads s1, s2, s3, s4 and S5 in FIG. 3, as Well as the corresponding pulses in the relay coils 1, 1', 2, 2', 3, 3'.

It will be seen from Table 2 that the combination of three flipflops constituted by the relays 1 and 1', 2 and 2', 3 and 3' performs a change of state in at least one of them until six pulses are counted, whereafter no further change takes place until the entire pulse sequence is terminated and the register B1 is reset. The result of these operations, in conjuntcion with the performance of the other system components, will be further explained with reference to a numerical example, after describing the quinary counter A1.

As will be seen from FIG. 3, all of the flip-flops 1-1', 2 2', 33 which in register B1 are in the on state at the end of any pulse sequence, are reset to the olf state when, shortly after termination of the sequence, the relay DS in device G1 drops oit` (see FIG. 4) and thus opens the contact ds in device E1, thus deenergizing any proviously energized relay circuits.

The quinary ring counter A1 is composed of three iipflops consisting of the relays A and B, C and D, E and F. In the following these dip-flops will be designated AB, CD and EF respectively. When a pulse is offered on lead s6 (FIG. 3) by closing of pulse contact i, the ip-tiop AB changes its state. When a pulse is offered on lead s7, the ip-op CD changes its state, while dip-flop EF does so when a pulse appears on lead S8. The counter A1 has five stable states indicated in Table 3.

4- 05.--. 05---- On. 011--.- 011--.- O6.

Suppose that relay P in summing device F1 (FIG. 3) is deenergized as shown. Then the following Table 4 indicates Whether a pulse applied to lead s1 will appear on lead s6, s7 or S8.

TABLE 4 Lead State .s6 s? x8 0 Yes No. No. Yes. Yes No. Yes.-- No No. 3 Yes-.. Yes-.. Yes. 4 No No Yes.

The conditions represented by Table 4 follow from the fact that the relay P of device F1 closes its two p contacts in counter A1. Taking, for instance, state 1 according to Table 4, it will be seen from Table 3 that the ip-flops AB and CD must change their respective states to reach state 2 (Tables 3 and 4). During the one pulse which shifts the ring counter A1 from the original state 0 to state 1, the relays B, D and F in counter A1 remain in the original state, so that the corresponding contacts b, d and f in counter A1 retain the positions shown in FIG. 3. Pursuing the sequence of pulses in the same manner through an entire quinary cycle, it will be seen that the following diagram of states for counter A1 is embodied in the counting operation, corresponding to an additive performance:

TABLE 5 Lead 4 i Yes... Yes." Yes.

Accordingly the diagram of states then also changes and may be represented as follows:

This shows that the quinary counter A1 counts the pulses on input lead s1 in the clockwise sense when relay P is oft", and counterclockwise when relay P is on.

A pulse-time diagram for the quinary counter A1 relating to additive counting (relay P energized) is shown in FIG. 5 in the same fashion as the above explained pulse diagram of FIG. 4, and with reference to the leads s1, s6, S7, S8 and relays A to F shown in FIG. 3. FIG. 6 is a corresponding pulse-time diagram for subtractive counting of the quinary counter A1 (relay P deenergized). Both diagrams exemplify a sequence of 8 pulses being dialed and thus appearing inverted on the pulse lead s1.

As mentioned, the device L1 shown in FIGS. l and 3 permits determining the check numeral after the number or character group has been entered without the check digit. As shown in FIG. 3, the device L1 in the illustrated embodiment is essentially an electrical replica of a matrix in which the ten digit values from 1 0 are represented by indicators such as numbered lamps which in FIG. 3 are shown only as numerals 1 0. These indicators are interwired with a current supply under control by the various relay contacts so as to indicate the proper check numeral upon entering of all preceding digits, it being only necessary to actuate a push button PBC.

The second indicator device M1 serves to check whether the entered group of numerals, including the check symbol, is correct. This device has a normally open check key CHK wired to an indicator signal CS, such as a lamp, through relay contacts a, c, e, k and g as shown in FIG. 3. After entering all digit values, the attendant depresses the key or push button CHK, and the signal CS will then respond only if the entered number with the check numeral is correct.

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N umercal example TABLE 6.--COUNTER STATES FOR NUMERAL 39059 Digit Position Digit Value C1 D1 A1 4..-. 5= Check Symbol.

All three pulses from dial K1 are counted by counter A1 (FIGS. 1, 3, 7). Since `C1 and D1 are in the same positions, counter A1 will substrtct. (It should be noted that counter A1 may also be made to add, as long as the operations adding and subtracting art consistently performed for given respective conditions of Cl/Dl). During the three pulses, the device G1 (time relay DS is FIG. 3) remains energized (FIG. 7). At the end of the pulse sequence, the counter A1 is at 2. Since 0-3 (mod 5)=2, C1 changes its position, D1 remains at 0. At the end of the rst pulse sequence, C1 is at 1, D1 is at f 0, and A1 is at 2 (FIG. 7, Table 6).

We now dial the second digit 9. K1 issues nine pulses (FIG. 8). G1 issues a single pulse whose length corresponds to the entire sequence of 9 counting pulses. The 6-bit counter B1 is always reset by G1 at the end of a pulse sequence. Hence, when entering the digit value 9, the counter B1 starts counting from zero and reaches the end position at the end of the sixth pulse from K1 (FIG. 8). The device E1 is so designed that when C is at 1, the setting of D1 is changed only -at the end of the signal from G1, provided B1 had reached the end position, i.e., had counted 6 steps. As a result, neither D1 nor C1 perform any operation during the entire sequence of nine pulses. However, all nine pulses are counted by the quinary counter A1 in the sense determined by the initial settings of C1 and D1 which were at l and at 0 respectively. That is, all nine pulses were counted additively. The counter A1 started out at 2. Since 2|-9(\mod 5)=1, the new position of counter A1 is 'at 1 after entering the second digit (FIG. 8, Table 6).

The third digit value is 0. K1 issues ten pulses (FIG. 9). The device G1 stays on for the entire duration of the ten pulses. `Counter B1 counts six pulses and then goes to the on position which it retains till the end of the entire sequence. `Counter C1 starts from the 0 position and is switched to position l only at the end of the entire sequence when the counter C1 receives a switching signal from G1. The counter D1 starts from position l. As soon as the counter B1 reaches its end position, it switches the counter D1 to position 0 because at that moment the counter C1 is also in the position 0, and the device E1 switches D1 immediately when counter B1 is in its end position if the counter C1 is simulaneously in position 0. Counter `C1 in effect counts the number of digits (mod 2), and counter D1 counts the occurrence of digits whose numerical value is above (O being considered to have the value 10). When C1 is in position l, it delays the counting operation of D1 until the end of the sequence signalled by G1. Counter A1 commences to start adding the rst six pulses of the sequence, but when D1 changes its position (FIG. 9), tht counter A1 starts to subtract the remainder of four pulses. Counter A1 started in position l (Table 6 After adding 6, it has reached the position 1-|-6(mod 2)=2. From this it substracts 4. Thus 2-4(mod 5)=3 is the end position of A1.

The fourth digit is 5. FIG. l0 indicates the operation of K1, B1, C1 and D1. B1 does not count up to six steps and therefore does not change its condition. `C1 starts in position 1 and changes to position 0 at the end of the sequence when receiving a signal from G1. D1 starts at 0 and does not change its position, because B1 does not change. At the end, C1 is at 0, D1 is at O and A1 has added ve steps 3-l-(mod 5)=3 (Table 6).

We have now dialed all but the last digit of the chosen numeral 39059. This last digit constitutes the added check symbol. Hence it cannot be arbitrarily chosen but is xed for given checking conditions. In the present example, the checking conditions require that after entering the entire numeral including the added check numtral, the quinary counter A1 shall be at zero, and the counters C1, D1 are to be in the same positions (O, 0 or l, 1) respectively. Based on these conditions, the matrix shown in Table 7 can bet set up, showing in the column A1 the position reached by counter A1 by entering the penultimatt digit and showing in the horizontal top row the four possible positional relations of Cl/Dl.

TABLE 7.-CHECK NUME BALS E Cl/DI The check digit can simply be taken from the cornputed Table 7. Since the penultimate (fourth) digit placed A1 at 3 and Cl/Dl at 0/0 (Table 6), we nd from Table 7 that the last (check) digit must be 9.

Of course, the matrix of Table 7 can be embodied by correspondingly wired electrical components (device L1 in FIGS. l Vand 3), so that we need only actuate a pushbotton contact PBC of decice L1 (FIG. 3) to make it indicate the check numeral, as will be more fully described hereinafter. p

If we now dial the check numeral 9, the following happens (FIG. ll, Table 6). Since C1 started at 0, the position of D1 changes as soon as the six-bit counter B1 reaches the end position. Since C1 and D1 were in the same 0 positions during the first six pulses, the counter A1 starts to subtract six pulses. The seventh, eighth and ninth pulses are then added because now C1 and D1 are in respectively different positions: 3-6+3(mod 5)=0. Thus entering the check numeral 9 results in placing the counter A1 at 0. At the same time, the counters C1 .and D1 are both at l, i.e. both in the same positions. This is indicative of the correctness of the entered number.

It should be understood that the above-described example of performing a check with counter A1 ultimately at 0 and counters C1 and D1 ultimately in the same respective positions is arbitrary. There are a total of ten different possibilities of checking of which any one may be selected. That is, the check may be made for counter A1 in any of the other four states (l, 2, 3, 4) and for counters C1, D1 in either the same states (0/0, 1/1) or in different states (O/l, 1/0). Once a set of these ten available combinations of conditions is chosen, a corresponding matrix of check numerals will result, and a check numeral satisfying one chosen set of conditions does not apply to another set.

Reverting to the numerical example, if any error is made Within a single digit of the number by exchanging two adjacent ldigits for each other, the entering of the number with the check symbol will not result in the prescribed iinal result in which A1 is at 0 yand C1, D1 are in the same positions. This holds true if the error concerns the check symbol alone, or if it resides in confusing the check symbol with the adjacent digit value.

Second embodiment (FIG. 2)

As mentioned, the system schematically shown in FIG. 2 is also based upon the Equations l and 2. In this device the numerals for the respective digit positions of the number, including the check numeral, are entered in parallel relation by respective pulses passing through separate conductors 1 0, one for each of the ten numerals. For entering each numeral, one of the ten keys of a keyboard K2 is to be depressed. The apparatus comprises ring counters A2, C2 and B2 in the moduli 5, 2 and 2 respectively. Also provided is a code converter H2. The output device M2 indicates in a suitable manner whether the entered number with the check numeral is correct or false, and the output device indicates the check numeral if the number `alone is entered into the keyboard K2.

Upon depressing a key of keyboard K2, a pulse passes through an OR gate OGC to the ring counter C2 which counts the supplied numerals (digit positions) in modulus 2. For numerals 6, 7, 8, 9 and 0 the pulse passes additionally through another OR gate OGD to the ring counter D2 whose state, therefore, represents For any of the entered numerals, a pulse is also supplied through the corresponding one of the ten conductors 1 0 to the code converter H2 which has two further inputs s11; s12 connected with the respective outputs of the binary ring counters C2 and D2. Also for each entered numeral, a pulse is supplied to one of the inputs S13 of the ring counter A2 operating in modulus 5 providing the algebraic addition (mod in accordance with the Equation 2. It is to be calculated from this equation how may states of the counter A2 must be suppressed, commencing from the state of the counter D2 which represents the sum (mod 2) of the binary components of the already supplied numerals, and based upon the state of the counter C2, i.e. the number j (mod 2) of the already supplied numerals, when the next following key is being depressed. The result of the calculation with respect to the number of steps located between the old and the new state of the counter is apparent from Table No. 8.

TABLE 8 If counter C2 was in the O-state and counter D2 in the l-state, the quinary counter A2, according to the tabulation, must occupy the state 1 when the key 8 is being depressed; if both counters C2 and D2 were in the O-state when key 8 is being depressed, three states of the quinary counter A2 must be suppressed so that the counter A2 will occupy the state 4. When depressing the key 5, no change in the O-state of the counter A2 must occur regardless of the states occupied by the respective binary counters C2 and D2.

To meet these requirements, the system is provided with the code converted H2 which has four outputs Z1, Z2, Z3, and Z4 connected with respective four inputs of the quinary ring counter A2. When depressing a key in keyboard K2, there appears a change in voltage on none, or a selected one of the outputs Z1 to Z4 which produces the desired suppression of states in counter A2. A voltage change in output Z4 results in a suppression of three counting states and thus sets the counter A2 four steps ahead when a key is being depressed.

When the counter A2 is equipped with transistor stages, the operation just described can ge secured, for example, by taking care that the supply of the pulse is effected through capacitors to the bases of the transistors. Connected to both sides of such capacitors must be the outputs of other transistor stages as well as outputs of the code converter H2. In this manner the supply of a pulse can be made to cause only the one desired counter state.

The entering of a digital number with a check numeral must bring the counter A2 to the zero state (or other pre-selected state). As a further criterion, it may be assumed, in accordance with Equation 1 that the binary counter D2 must also be in the zero state. The output members L2 and M2 are correspondingly controlled from the counters A2 and D2.

Instead of having the counter C2 add the supplied numerals in modulus 2, the counter may also be used for determining the number of numeral pulses augmented by the modulo 2 sum of the binary components of the numeral, which results in the same sum as obtained in the summing device F1 in FIG. 1. In this case, when setting up a table in analogy to Table 8, the states which the quinary counter A2 must indicate are to be related to the old C2/D2 counter states 0/0, l/l, l/O and 0/1.

The embodiment according to FIG. 2 ajords greater flexiblity in comparison with that of FIG. 1 because it can be readily changed for a different assignment of the values a and e. lf one wants to use a different function for those terms of the second equation which depend only upon e, then the embodiment of FIG. 2 can likewise be readily adapted accordingly. In both cases, the number of counting steps for the counter A2 in Table 8 must be 16 changed, which requires an exchange of a few electrical connections in the logic circuitry. In the former case, it is also necessary to supply a pulse to the counter D2 for different numerals, which involves connecting these other conductors with the OR-gate OGD preceding the counter Devices according to FIGS. 1, 2 and 3, of course, may be equipped with a variety of modular components, such as relays, tubes, transistors, diodes, well known and commercially available for such purposes. This will be exemplified by the embodiment of the systems shown in FIGS. 12 to l5 and described presently.

Third embodiment (FIGS. 12 to 15) The system illustrated in FIGS. 12 to l5 utilizes the invention for controlling an accounting machine in such a manner that the machine will commence operating only if an initially posted multi-digit number, such as the account number of a customer, is correct. Since the system is based upon fundamental features described above with reference to FIG. 2, it will be helpful to briefy recapitu late some of these features.

In the system of FIG. 2 a multi-digit decimal number is checked by computing a check symbol (Z) which is taken from the available ten numerals 1 0 and added to the number as the last digit thereof. The individual digit Values are then added in modulus 5 and a check made as to whether the result in equal to zero, and whether the modulo-2 sum of those digit positions whose respective values are more than 5 is also equal to zero. The added check numeral (Z) depends upon two binary input variables C2 and D2, which in FIG. 2 are counted by respective modulo-2 counters C2 and D2. C2=l for each even odd digit position, and C2:0 for each digit position. The value of D2 indicates the modulo-2 sum of the digits in which the digit value is more than 5. When the digit positions of a higher value than 5 amount to an even number, the value of D2=0; Iwhen the number of these digit positions is odd, the value of D2=1. The additional check numerals Z are listed in Table 8.

The modification system of FIGS. 12 to 15 incorporates a somewhat different correlation of counter positions and check numerals, as will be explained presently. The following Table 9 corresponds to Table 8, except that a horizontal division line is inserted between numerals 5 and 6 in the rst vertical column denoting the entered decimal digit values. As a result, Table 9 then comprises eight groups of tive check numerals Z.

TABLE 9 Numeral Entered Check Values Z Old State 0/0 0/1 1/0 1/1 Ce/Dz (zz) (C2132) (C252) (C2132) It will be seen that the three groups denoted by are identical. Three other groups, denoted by are also identical among themselves; and there are two additional groups denoted by and Consequently, there are only four different groupings of check numerals, namely the groups and For distinguishing between the upper and the lower half of the Table 9 (numerals 1 to 5 and numerals 6 to 0), we introduce two further input variables Q (for numerals above 5) and 'Q (for numerals l to 5).

1 7 Consequently, the automatic computation of the check numerals can be effected in a four-group matrix as shown in Table 10.

TABLE 10 Cz/Dn A B C D Z1 Z4 Zl Z4 The matrix of Table l0 is incorporated in the code converter H3 of the system shown in FIGS. l2 to 14, described presently. As regards the pulse sequences occurring in the system, reference may be had to FIG. 15.

In FIG. 12, the matrix MA1 is schematically represented in the same manner as Table l0, whereas FIG. 13 shows its electrical replica in detail. The performance of this matrix in conjunction with the other components of the same system will be apparent from the following description with reference to FIG. 12.

The accounting machine to be controlled by the selfchecking system comprises a keyboard K3 with ten pushbutton contacts per digit position of the decimal number to be checked. In the present embodiments the keyboard capacity is for a number of ten digit positions. In addition, the keyboard has a vertical row ZP of of push-button contacts for posting a check numeral. When no number is posted, 0 contacts (bottom row) of the ll columns Zz`1 to Zz'10 and Zz'P are closed as shown. When a numeral is posted into any one digit position, the one contact corresponding to the posted digit value closes.

After the entire number, including the check digit, is posted, the attending person must depress a test key CHK which forms part of the device M1 corresponding to the equally designated device in FIG. 1. When the posted number is correct, the closing of key CHK has the result that a relay ONR in device M1 is energized and closes a contact onr which completes a circuit between plugs PAM and thereby releases the machine control so that the accounting machine will commence operating. If the posted number is incorrect, the contact onr does not close and the accounting machine will not start.

The just-mentioned discriminating performance of the ONR relay depends upon the result of the computation effected within the checking system. This computation takes place as follows.

The closing of the test key CHK energizes a relay PR whose contact pri prepares the relay ONR for operation by connecting it to ground (zero voltage). A second contact pf2 connects zero voltage to a monostable multivibrator MOV and simultaneously to an inhibit gate UG1. The multivibrator MOV supplies a pulse of about 5 milliseconds duration. During the pulse, the gate UG1 is blocked to prevent faults due to contact bouncing. Within the interval of 5 milliseconds, the pulse from the multivibrator MOV is supplied through the lead NO to other system components with the following elfects:

(l) In a shift register SHR the pulse, entering through lead N1, sets the first core 1 or other register unit.

(2) A iiip-flop FD receives the pulse through lead N2 and is thereby reset to the O-state.

(3) In a 5bit memory SBM, the pulse, supplied through lead N3, sets the 0-core and resets the cores 1-4 to the 0-states.

After termination of the 5 milliseconds pulse from MOV, the inhibit gate UG1 opens so that a square-wave generator SQG is switched on to furnish a frequency of approximately kilocycles per second. The synchronizing or clock pulse from SQG is supplied through synchronizing leads T to the shift register SHR and an AND- gate UG10. Each clock pulse shifts the set condition of the rst core one position forward in the shift register SHR. Thus, the leads Zi1 to Zi10, ZP and P sequentially receive one current pulse each.

Depending upon which particluar contact is closed in the respective digital columns, the pulse is issued to ten output leads of the keyboard K3. The tive output leads corresponding to the respective digit values 1 and 6 are connected to the respective two inputs of an AND-gate VG4. In the same manner, the output leads 2 and 7, 3 and 8, 4 and 9, 5 and 0 are connected in pairs to the respective inputs of AND-gates VGS to VGS. Thus, only ve output leads from the respective AND-gates VG4 to VGS reach the above-mentioned matrix MA1 where they become interlinked with the separately supplied auxiliary variables A, B, C, D in accordance with the truth table shown at MA1 in FIG. l2 corresponding to Table l0.

For producing the auxiliary variables A, B, C, D, the command C2 is derived from the even digit positions of the number posted into K3, and the command O2 from the odd digit positions of the number. The digit values from l to 5 result in the command and the digit values of 6 to 0 result in the command Q, as has been explained in the foregoing.

The command Q is accordingly taken from an AND- gate VG9 whose respective inputs are connected with the ve output leads of the keyboard K3 that corresponds to the digit values 6 to 0, and the output of gate VG9 furnishes the command pulse Q to the flip-flop FD. The end ank of the pulse Q switches the ip-flop FD each time to the other state; that is, in the ip-ilop FD the binary components of the posted number are added in modulus 2.

Analogously, the command pulse appears as the output of an AND-gate VG3 which has live inputs connected with those respective output leads of keyboard K3 that correspond to the digit values 1 to 5. The outputs of gates VG3 and VG9 are connected with the respective input of an AND-gate VG10. The output of the gate VG10 is connected to respective inputs of two AND-gates UG2 and UG3 whose other inputs are connected -with the respective outputs of the ip-op FD. The AND-gates UG2 and UG3 furnish the commands D2 and D2 respectively. Depending upon the state of the ip-flop FD, the command pulses Q or C) result in issuing the respective commands D2 and D2.

A logic network LN composed of AND-gates UG4 to UG9, VG11 and VG12 serve to compute the auxiliary variables A, B, C, D from the commands C2, O2, D2 D2, Q, in accordance with the above-presented equations. This logic network LN and the matrix MA1 jointly constitute a code converter corresponding in principle to the code converter H2 in FIG. 2.

The check value pulses appearing on the four output leads Z1 to Z4 of the matrix MA1 are supplied to the matrix MAZ which interlinks the check values with the 

